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NXP Semiconductors /LPC18xx /GPDMA /C0LLI

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Interpret as C0LLI

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AHB_MASTER_0_)LM 0 (R)R0LLI

LM=AHB_MASTER_0_

Description

DMA Channel Linked List Item Register

Fields

LM

AHB master select for loading the next LLI:

0 (AHB_MASTER_0_): AHB Master 0.

1 (AHB_MASTER_1_): AHB Master 1.
R

Reserved, and must be written as 0, masked on read.
LLI

Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data